In this tutorial, we’ll learn about clock mechanism in LPC2148. Here we’ll discuss every detail about configurations of Clock and PLL in LPC2148 ARM7 Microcontroller. There are several ways we can clock ARM Microcontroller. One way is to use External Clock with duty cycle 50-50 and in a frequency range 1 MHz to 50 MHz connected to XTAL1 Pin. The second way is by connecting External Crystal Oscillator but its range is lower between 1 MHz to 30 MHz. We can also use on-chip PLL Oscillator but here external clock frequency should not exceed range from 10 MHz to 25 MHz. In this tutorial, we will concentrate on External Crystal with PLL. External Clock source and External Crystal only will be discussed in future since it’s not required at this moment.
Mechanism: PLL in LPC2148 ARM7
What is PLL (Phase Lock Loop)?
PLL is used to generate system clock from between 10 MHz to 25 Mhz. PLL may multiply frequency to range from 10 MHz to 60 MHz (LPC21xx Series) and 48 MHz for USB if used. PLL uses frequency multiplier which can be in a range from 1 to 32, in real world situation this value should not be higher than 6 due to upper frequency limit. PLL generator allows running ARM at high speed with low frequency oscillator connected. Also, this minimizes EMC emission as frequency is multiplied inside ARM Chip. PLL allows changing frequency dynamically. In LPC2148 microcontrollers there are two PLLs which provide programmable frequencies to the CPU and USB System. [PLL0: For System Clock, PLL1: For USB Clock]
ARM7 LPC2148 Microcontroller needs two clocks; one is for its peripherals and other for its CPU. CPU works faster with higher frequencies whereas peripheral needs lower frequency to work with. The Peripheral Clock (PCLK) and CPU Clock (CCLK) gets clock input from a PLL or from external source. After RESET, configuration of PLL (Phase Lock Loop) and VPB (VLSI Peripheral Bus) Divider would be first thing to do.
PLL unit itself uses CCO (Current Controlled Oscillator) which operates in the range between 156 MHz to 320 MHz, so there is additional divider which keeps CCO within its range, while PLL provides desired frequency. Output clock is generated by dividing CCO frequency by 2, 4, 8, 16. Minimum divider is ‘2’ so output of PLL will always have duty cycle 50% for sure.
The Peripheral Clock i.e. PCLK is derived from CPU Clock i.e. CCLK. The APB Divider decides the operating frequency of PCLK. The input to APB Divider is CCLK and output is PCLK. By Default PCLK runs at 1/4th the speed of CCLK. To control APB Divider we have a register called VPBDIV. The value in VPBDIV controls the division of CCLK to generate PCLK as shown below:
|VPBDIV=0x00||APB bus clock (PCLK) is one fourth of the processor clock (CCLK)|
|VPBDIV=0x01||APB bus clock (PCLK) is the same as the processor clock (CCLK)|
|VPBDIV=0x02||APB bus clock (PCLK) is one half of the processor clock (CCLK)|
|VPBDIV=0x03||Reserved. If this value is written to the APBDIV register, it has no effect (the previous setting is retained).|
PLL Registers in LPC2148
PLL Registers are listed here, for more details follow datasheet:
PROGRAMMING: PLL in LPC2148 ARM7
While configuring clock and PLL in LPC2148 ARM7. We have to follow general steps. It’s important to follow sequence to perform configuration part of PLL
- Select the desired operating frequency for your system (CPU Operating Frequency) CCLK
- Check the oscillator connected to the controller on board FOSC
- Calculate the value of PLL Multiplier ‘M’ CCLK=M x FOSC
- Find the value of PLL Divider ‘P’ in such a way that is in the range of 156 MHz to 320 MHz, 156<FCCO<320 = CCLK x 2 x P
- Write the value PLLCON and PLLCFG
- Write the PLLFEED values 0xAA and 0x55
- Wait for PLL to lock
- Connect the PLL
- Write the PLLFEED values 0xAA and 0x55 once again
EXAMPLE: Setting PLL in LPC2148
We have 12 MHz crystal connected to LPC2148 on our microcontroller development board. We can say FOSC=12 MHz. And we want core to be run at 60 MHz. In this case, we have to multiply crystal frequency i.e.12 MHz by ‘5’
|CCLK = M x FOSC = 5 x 12 = 60 MHz|
Also we have to keep FCCO (Frequency of the PLL Current Controlled Oscillator) within its range i.e. [156 MHz – 320 MHz], so we have to control another constant ‘P’:
|FCCO = CCLK x 2 x P|
|FCCO = 60 MHz x 2 x 2 = 240 MHz|
So we found P = 2 meets FCCO requirements (156 MHz Programming PLL has to be done in some sequence to make new PLL setting effective. First of all we have to write multiplier M and divider P values to PLLCFG Register. Since M & P values can be very specific. As shown in table below
So for our calculation M = 5 and P = 2, then PLLCFG = 0b00100100 = 0x24;
Further, there has to follow some sequence to activate PLL. After PLLCFG register is updated then update PLLCON register and then we have to write 0xAA and then 0x55 to PLLFEED register. This value has to be written in consecutive cycles. Here is an example.
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked?
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; // PCLK is same as CCLK i.e.60 MHz
This is how you can configure Clock and PLL in LPC2148 ARM7 Microcontroller. In next tutorial, we’ll explore timer feature in LPC2148 ARM7 where we’ll explore the usage of PLL with an example project. If you have any question, then feel free to leave a comment. Thanks.
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