Friday , August 23 2019

Learn ARM Cortex-M3 LPC1768 Microcontroller Architecture

In this post, we’ll learn ARM Cortex-M3 LPC1768 Microcontroller architecture. I have decided not to go deep into theory part because there is no point repeat datasheet. Instead, I would like to focus on fundamentals, registers, operation modes and so on. I recommend readers to hold datasheet to get more inside. As we move along with this tutorials series you will feel comfortable to work with Cortex-m3 LPC1768 Microcontroller. The Contex-M3 is 32-bit Microprocessor. It has 32-bit data path, 32-bit register bank and 32-bit memory interfaces.

Cortex-M3 LPC1768 Microcontroller

The Cortex-M3 offers many new features including Thumb-2 Instruction Set and very low power consumption, low interrupt latency etc. I will cover those in future. The LPC1768 is microcontroller belongs to Cortex-M3 core. LPC1768 is mixed signal processor from NXP Semiconductor.

The processor has Harvard Architecture, which means it has separate instruction bus and data bus. This allows instruction and data access take place at the same time which results in higher performance. However instruction and data buses share same memory for complex application where more memory is primary need, the Cortex-M3 processor has an optional MPU. I would like to point out some features which make Cortex-M3 LPC1768 stand out from previous generation processors.



Harvard Architecture makes chip high performance. Thumb-2 instruction set. Operates at high frequency up to 100MHz


Low gate count. Sleeping mode and deep sleeping mode available for power saving


Provide bit band operation, byte-invariant big endian mode and unaligned data access support. Fault handling features and optional MPU (Memory Protection Unit)


  • The built-in NVIC
  • Reduced IRQ handling latency
  • Allows to change interrupt priority in runtime


  • Support JTAG or serial wire debug interface
  • Processor status or memory contents can be access driven when the core is running
  • Built-in support for six breakpoints and four watch points
  • Optional ETM for instruction trace and data trace using DWT
  • New debugging feature, including fault status register, new fault exceptions and flash patch operations which makes debugging much easier
  • ITM provides an easy to use method to output debug information from test code
  • PC sampler and counters inside the DWT provide code profiling information
Simplified View: Cortex-M3 Architecture

The on-chip peripheral components of LPC1768 include Ethernet MAC, USB interface that can be configured as either HOST, Device or OTG, 8-channel general purpose DMA controller, 4-UARTs, 2-CAN channels, 2-SSP controllers, SPI interface, 3-I2C interfaces, 2-Input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder Interface, 4-general purpose timers, 6-output general purpose PWM, Ultra-low power RTC with separate battery supply and upto 70 general purpose IO pins. It supports the operating system like Windows CE, LINUX, Palm OS and so on.

Cortex-M3 Processor is Load/Store Architecture with Three Basic type of Instruction:

Register-to-Register-operation for processing data
Memory Operation– which move data between memory and register
Control Flow– operations enabling programming language control flow such as if and while statements and procedure calls.

I think this much is enough for this tutorial. Now you are familiar with basics of Cortex-M3 Core. In next tutorial, I’ll introduce you programming software and hardware require to program NXP LPC1768 Microcontroller. I hope you will find this tutorial educational and entertaining see you in next tutorial.

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About Umesh Lokhande

Umesh Lokhande holds a Master degree in Scientific Instrumentation from University of Applied Sciences Jena, Germany. and has previously worked at Orbotech, Alere Technologies etc. Umesh is also a founder and first author of BINARYUPDATES.COM


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